EP2A25F672C7 vs EP2A25F672I-9 Сравнение
Подробное сравнение бок о бок EP2A25F672C7 от Altera и EP2A25F672I-9 от Intel. Сравните ключевые характеристики, электрические параметры, упаковку, статус жизненного цикла, цены и наличие, чтобы выбрать лучший компонент для ваших требований.
Сравнение характеристик
| Параметр | EP2A25F672C7 | EP2A25F672I-9 |
|---|---|---|
| Бренд | Altera | Intel |
| Категория | FPGA & CPLD | FPGA & CPLD |
| Статус жизненного цикла | NRND | Obsolete |
| Наличие | In Stock | In Stock |
| Цена за единицу (USD) | $118,00 | $195,00 |
| Product Family | APEX II | — |
| Logic Elements | 25,000 | — |
| Maximum System Gates | 1,650,000 | [DATA_NEEDED: maximum system gates] |
| Maximum RAM Bits | 422,976 | — |
| User I/O Count | 492 | — |
| Корпус | 672-ball FCBGA (FineLine BGA) | 672-pin FCBGA (FineLine BGA) |
| Process Technology | 0.15-um all-layer copper, up to 8 metal layers | 0.18 µm CMOS |
| Supply Voltage (Core) | 1.5 V | — |
| LVDS Data Rate | 1 Gbps per channel (True-LVDS) | — |
| I/O Standards Supported | LVDS, LVPECL, PCML, HyperTransport | — |
| Рабочая температура | 0C to +85C (Commercial) | — |
| Speed Grade | -7 | -9 |
| Configuration Mode | Passive Serial, Passive Parallel, JTAG | — |
| Статус RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Embedded System Blocks (ESB) | Yes - RAM, ROM, CAM, multiplier support | — |
| Family | — | APEX II |
| Logic Elements (typical) | — | 25,000 |
| Embedded System Blocks (ESB) Memory | — | 1,125 Kbits |
| Maximum User I/O Pins | — | [DATA_NEEDED: maximum user I/O pins] |
| Number of PLLs | — | 4 |
| Core Voltage | — | 1.5 V / 1.8 V (speed-grade dependent) |
| Operating Temperature Grade | — | Industrial (-40 °C to +100 °C junction) |
| Тип монтажа | — | Surface Mount (BGA) |
| Уровень чувствительности к влаге (MSL) | — | 3 (per Vyrian listing) |
| Peak Reflow Temperature | — | 220 °C (per Vyrian listing) |
| Configuration Method | — | JTAG / serial configuration EPROM |
| Supported I/O Standards | — | LVTTL, LVCMOS, LVDS, PCI |
| Legacy Status | — | Obsolete - consult Altera / Intel FPGA archive for documentation |