EP2A40F672C9ES vs EP2A40F672C6N Comparación
Comparación detallada lado a lado de EP2A40F672C9ES por Altera y EP2A40F672C6N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP2A40F672C9ES | EP2A40F672C6N |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $195,00 | $165,00 |
| Family | APEX II | APEX II |
| Logic Elements | 38,400 | 40,000 |
| System Gates | 1,500,000 | — |
| Maximum User I/O | 492 | — |
| Operating Frequency (max) | 366 MHz | — |
| Process Technology | 0.15 µm CMOS | SRAM-based, 0.18 um (per family datasheet) |
| Core Voltage | 1.5 V | 1.5 V |
| Encapsulado | 672-pin FC-FBGA | 672-ball FineLine BGA |
| Tipo de montaje | Surface Mount (BGA) | Surface Mount |
| Speed Grade | -9 | C6 (per part number suffix) |
| Configuration Modes | PS, PPS, PPA, JTAG, FPP | — |
| Embedded Memory (ESB) | Yes (RAM/ROM/CAM) | — |
| I/O Standards | LVTTL, LVCMOS, PCI, SSTL, HSTL, GTL+ | — |
| Boundary Scan | IEEE 1149.1 (JTAG) | — |
| Estado RoHS | unknown | [DATA_NEEDED: RoHS compliance status] |
| Maximum System Gates | — | 1,125,000 |
| Embedded RAM Bits | — | 442,368 |
| Embedded System Blocks (ESBs) | — | 160 |
| Maximum User I/O Pins | — | [DATA_NEEDED: maximum user I/O count] |
| I/O Standards Supported | — | LVTTL, LVCMOS, PCI, GTL+, SSTL, HSTL, 1.8V/2.5V/3.3V/5V |
| Temperatura de funcionamiento | — | Commercial (0C to +85C) |
| Configuration Methods | — | Passive Serial, Passive Parallel, JTAG |
| PLL Count | — | [DATA_NEEDED: PLL count] |