EP2AGX125EF35C4G vs EP2AGX95EF35C4G Comparación
Comparación detallada lado a lado de EP2AGX125EF35C4G por Intel y EP2AGX95EF35C4G por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
EP2AGX125EF35C4G - Arria II GX FPGA, 118K LEs, 1152-FCBGA | Intel
EP2AGX125EF35C4G ⚠ Última compra
Comparación de especificaciones
| Parámetro | EP2AGX125EF35C4G | EP2AGX95EF35C4G |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Última compra | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $1.290,00 | $1.555,00 |
| Family | Arria II GX | Arria II GX |
| Logic Elements | 118,143 | — |
| Embedded Memory Bits | 8,315,904 | 6,839,296 bits (~6.5 Mbit) |
| Memory Blocks (M9K) | [DATA_NEEDED: M9K count] | — |
| Hardware Multipliers (18x18) | 452 | — |
| DSP Blocks | [DATA_NEEDED: DSP block count] | — |
| Transceiver Channels | 12 | — |
| Maximum Transceiver Data Rate | 6.375 Gbps | — |
| PCI Express Hard IP | Gen1/Gen2 x1/x4/x8 | — |
| Core Voltage | 0.9 V | 0.9 V nominal |
| User I/O Banks | [DATA_NEEDED: I/O bank count] | — |
| Maximum User I/O | [DATA_NEEDED: max user I/O count] | — |
| Process Technology | 40 nm | 40 nm TSMC low-power |
| Encapsulado | 1152-ball FC-FBGA (Flip-Chip) | 1152-ball FCBGA, 35 mm x 35 mm, 1.0 mm pitch |
| Temperatura de funcionamiento | 0C to +85C (Commercial) | 0C to +85C (commercial) |
| Tipo de montaje | Surface Mount | — |
| Configuration Method | SRAM-based, PS/FPP/JTAG | — |
| Estado RoHS | Compliant | Compliant |
| Speed Grade | C4 | -4 (mid-speed) |
| Lead-Free | Yes | — |
| Logic Elements (LE) | — | 89,178 |
| Adaptive Logic Modules (ALM) | — | [DATA_NEEDED: ALM count from datasheet] |
| Embedded Memory Blocks (M9K/M144K) | — | [DATA_NEEDED: block count from datasheet] |
| Embedded 18x18 Multipliers | — | 616 |
| User I/Os | — | 452 |
| Transceiver Blocks | — | 4 (up to 3.75 Gbps) |
| PCIe Hard IP | — | Gen1/Gen2 (x1/x2/x4) |
| PLLs | — | 4 |
| Global Clock Networks | — | [DATA_NEEDED: per Arria II family datasheet] |
| Configuration Mode | — | Passive Serial, Fast Passive Parallel, JTAG |