EP2AGZ225FF35C3G vs EP2AGZ350FF35C3G Comparación
Comparación detallada lado a lado de EP2AGZ225FF35C3G por Altera y EP2AGZ350FF35C3G por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP2AGZ225FF35C3G | EP2AGZ350FF35C3G |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $868,40 | $2.680,00 |
| Family | Arria II GZ | Arria II GZ |
| Series | Arria II | — |
| Logic Elements (LE) | 225,000 | 350,000 |
| Encapsulado | 1152-ball Flip-Chip BGA (FF35) | 1152-FBGA (35 mm x 35 mm, 1.0 mm pitch) |
| Package Size | 35 mm x 35 mm | — |
| Temperatura de funcionamiento | 0C to +85C (Commercial) | 0C to +85C (commercial) |
| Speed Grade | C3 | — |
| Transceivers | Up to 16 channels | 8 |
| Transceiver Data Rate (max) | 6.375 Gbps | — |
| DSP Blocks | [DATA_NEEDED: count] | — |
| Embedded Memory | [DATA_NEEDED: Mbits] | 16,860 Kbits |
| User I/O Banks | [DATA_NEEDED: count] | — |
| Maximum User I/O | [DATA_NEEDED: pin count] | — |
| Process Technology | 40 nm TSMC | — |
| Memory Controller Support | DDR3, DDR2, QDR II+ | — |
| PCI Express Hard IP | Yes (Gen1/Gen2) | — |
| Estado RoHS | Compliant | Compliant |
| Tipo de montaje | Surface Mount (BGA) | Surface Mount (BGA) |
| Nivel MSL | 3 (per JEDEC J-STD-020) | — |
| Lead-Free | Yes | — |
| DSP Blocks (18x18 Multipliers) | — | 224 |
| Transceiver Data Rate | — | up to 6.375 Gbps |
| User I/O Pins | — | 554 |
| PLLs | — | 8 |
| Hard Memory Controllers | — | 2 |
| Memory Interface Support | — | DDR3, DDR2, QDR II+, RLDRAM II |
| Maximum Memory Clock | — | 800 MHz |
| Process Node | — | 40 nm TSMC |
| Core Voltage | — | 0.9 V |
| Configuration Modes | — | Passive Serial, Fast Passive Parallel, JTAG, AS |