EP2S130F1020C5ES vs EP2S130F1020C5N Comparación
Comparación detallada lado a lado de EP2S130F1020C5ES por Altera y EP2S130F1020C5N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP2S130F1020C5ES | EP2S130F1020C5N |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $1.380,00 | $1.320,00 |
| Family | Stratix II | Stratix II |
| Logic Elements | 132,540 | 132,540 |
| Embedded Memory Bits | 6,747,840 | — |
| Maximum User I/Os | 742 | — |
| Process Technology | 90 nm | 90 nm |
| Core Voltage | 1.2 V | — |
| Maximum Internal Clock Frequency | 609.76 MHz | — |
| Speed Grade | -5 | — |
| Encapsulado | 1020-ball FC-FBGA (flip-chip BGA) | 1020-ball FC-FBGA (33x33 mm) |
| Operating Temperature (Junction) | 0C to 85C (commercial) | — |
| Logic Array Blocks (LABs) | 6,747 | — |
| Adaptive Logic Modules (ALMs) | 53,016 | 6627 LABs (per Jotrin listing) |
| Total RAM Blocks | [DATA_NEEDED: total RAM blocks] | — |
| Embedded DSP Blocks | [DATA_NEEDED: embedded DSP blocks count] | — |
| Embedded 18x18 Multipliers | [DATA_NEEDED: 18x18 multiplier count] | — |
| PLLs | [DATA_NEEDED: PLL count] | 4 (typical Stratix II feature) |
| Configuration | SRAM-based, JTAG/AS/PS modes | — |
| Estado RoHS | Compliant (lead-free) | [DATA_NEEDED: rohs status] |
| Tipo de montaje | Surface Mount | Surface Mount |
| Total Memory Bits | — | 6,747,840 bits |
| User I/Os | — | 734 |
| Core Supply Voltage (VCCINT) | — | 1.15 V to 1.25 V |
| Maximum Internal Frequency | — | 609.76 MHz |
| Temperatura de funcionamiento | — | Commercial (0C to +85C, C5 grade) |
| Temperature Grade | — | C5 (other - per Partstack) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Global Clock Networks | — | 16 (typical Stratix II feature) |
| Configuration Method | — | Serial/Parallel via Quartus II (typical Stratix II) |
| Country of Origin | — | Republic of Korea (per GlobalSpec) |
| ECCN | — | 3A001.a.7.a (per GlobalSpec) |
| Estimated EOL Date | — | 2023 (per GlobalSpec) |