EP2SGX90FF1152 vs EP2SGX90EF1152I5N Comparación
Comparación detallada lado a lado de EP2SGX90FF1152 por Altera y EP2SGX90EF1152I5N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
EP2SGX90EF1152I5N - 90k LEs Stratix II GX FPGA 1.2V FC-FBGA-1152 | Intel
EP2SGX90EF1152I5N ObsoleteComparación de especificaciones
| Parámetro | EP2SGX90FF1152 | EP2SGX90EF1152I5N |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Última compra | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $1.425,00 | $1.320,00 |
| Series | Stratix II GX | EP2SGX90 |
| Family | FPGA | Stratix II GX |
| Logic Elements (LE) | 90,960 | — |
| Logic Array Blocks (LABs) | 4,548 | — |
| Embedded Memory (RAM bits) | 4,520,448 | — |
| User I/Os | 558 | — |
| Transceivers | Up to 20 channels | — |
| Transceiver Data Rate | Up to 6.375 Gbps | — |
| Core Voltage | 1.2 V | — |
| Process Node | 90 nm | — |
| Encapsulado | 1152-ball FC-FBGA (Flip-Chip) | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Estado RoHS | Compliant | [DATA_NEEDED: RoHS status] |
| Lead-Free | Yes | — |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature grade] | — |
| Logic Elements (LEs) | — | 90,960 |
| Equivalent CLBs | — | 90,960 |
| Process Technology | — | 90 nm CMOS |
| Core Voltage (VCCINT) | — | 1.2 V |
| Frecuencia de reloj máxima | — | 609.76 MHz |
| Combinatorial Delay | — | 4.006 ns |
| Package Type | — | FC-FBGA (flip-chip fine-pitch BGA) |
| Number of Pins/Balls | — | 1152 |
| Package Code | — | BGA |
| Package Shape | — | SQUARE |
| Terminal Form | — | BALL |
| Operating Temperature Grade | — | INDUSTRIAL (I) |
| Embedded Transceivers | — | Yes (GX series, multi-gigabit PMA) |
| On-chip Block Memory | — | [DATA_NEEDED: total M512/M4K/M-RAM bits] |
| DSP Blocks | — | [DATA_NEEDED: number of DSP blocks] |
| User I/O Banks | — | [DATA_NEEDED: I/O bank count] |