EP2SGX90FF1152 vs EP2SGX90EF1152I5N Comparaison
Comparaison détaillée côte à côte de EP2SGX90FF1152 par Altera et EP2SGX90EF1152I5N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
EP2SGX90EF1152I5N - 90k LEs Stratix II GX FPGA 1.2V FC-FBGA-1152 | Intel
EP2SGX90EF1152I5N ObsoleteComparaison des spécifications
| Paramètre | EP2SGX90FF1152 | EP2SGX90EF1152I5N |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Dernier achat | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $1 425,00 | $1 320,00 |
| Series | Stratix II GX | EP2SGX90 |
| Family | FPGA | Stratix II GX |
| Logic Elements (LE) | 90,960 | — |
| Logic Array Blocks (LABs) | 4,548 | — |
| Embedded Memory (RAM bits) | 4,520,448 | — |
| User I/Os | 558 | — |
| Transceivers | Up to 20 channels | — |
| Transceiver Data Rate | Up to 6.375 Gbps | — |
| Core Voltage | 1.2 V | — |
| Process Node | 90 nm | — |
| Boîtier | 1152-ball FC-FBGA (Flip-Chip) | — |
| Type de montage | Surface Mount | Surface Mount |
| Statut RoHS | Compliant | [DATA_NEEDED: RoHS status] |
| Lead-Free | Yes | — |
| Température de fonctionnement | [DATA_NEEDED: operating temperature grade] | — |
| Logic Elements (LEs) | — | 90,960 |
| Equivalent CLBs | — | 90,960 |
| Process Technology | — | 90 nm CMOS |
| Core Voltage (VCCINT) | — | 1.2 V |
| Fréquence d'horloge maximale | — | 609.76 MHz |
| Combinatorial Delay | — | 4.006 ns |
| Package Type | — | FC-FBGA (flip-chip fine-pitch BGA) |
| Number of Pins/Balls | — | 1152 |
| Package Code | — | BGA |
| Package Shape | — | SQUARE |
| Terminal Form | — | BALL |
| Operating Temperature Grade | — | INDUSTRIAL (I) |
| Embedded Transceivers | — | Yes (GX series, multi-gigabit PMA) |
| On-chip Block Memory | — | [DATA_NEEDED: total M512/M4K/M-RAM bits] |
| DSP Blocks | — | [DATA_NEEDED: number of DSP blocks] |
| User I/O Banks | — | [DATA_NEEDED: I/O bank count] |