EP3SE260H780C3 vs EP3SE260H780C3N Comparación
Comparación detallada lado a lado de EP3SE260H780C3 por Intel y EP3SE260H780C3N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
EP3SE260H780C3N - Stratix III E FPGA, 255K LE, 780-BGA | Intel / Altera
EP3SE260H780C3N ✓ ActivoComparación de especificaciones
| Parámetro | EP3SE260H780C3 | EP3SE260H780C3N |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $1.180,00 | $1.325,00 |
| Device Family | Stratix III Enhanced (Stratix III E) | — |
| Series | EP3SE | Stratix® III E |
| Logic Elements | 255,000 | — |
| Logic Array Blocks (LABs) | 10200 | — |
| Embedded Memory | 16,672,768 bits (16.67 Mbit) | — |
| User I/Os | 488 | 488 |
| Operating Voltage (Core) | 0.9 V | — |
| Operating Voltage (Auxiliary) | 1.1 V | — |
| Process Technology | 65 nm CMOS | 40 nm CMOS |
| Speed Grade | C3 | — |
| Temperatura de funcionamiento | Commercial, 0C to +85C | 0 °C to +85 °C (C grade, commercial) |
| Maximum Core Frequency | 500 MHz | [DATA_NEEDED: maximum core frequency MHz] |
| Encapsulado | 780-ball FCBGA (HBGA), flip-chip | 780-BBGA, FCBGA (H780) |
| Tipo de montaje | Surface Mount (BGA) | Surface Mount |
| Nivel de sensibilidad a la humedad (MSL) | 3 (168 hours) | [DATA_NEEDED: MSL level per JEDEC J-STD-020] |
| Packaging Type | Tray | — |
| Configuration Memory Support | Fast passive parallel, JTAG, Active Serial | — |
| Estado RoHS | Compliant (per product listings) | Compliant (lead-free 'N' suffix) |
| Logic Elements (LE) | — | 255,000 |
| Embedded Memory (bits) | — | 16,672,768 |
| Number of LABs/CLBs | — | 10,200 |
| Number of Pins / Balls | — | 780 |
| Supply Voltage (VCCINT) | — | [DATA_NEEDED: VCCINT nominal V] |
| Transceivers | — | [DATA_NEEDED: number of embedded transceivers and max data rate] |
| DSP Blocks | — | [DATA_NEEDED: number of DSP blocks and precision] |
| Configuration Method | — | SRAM-based, configured via JTAG / passive / active serial / fast passive parallel |
| Design Toolchain | — | Altera Quartus II (legacy); Intel Quartus Prime |