EP3SE260H780C3 vs EP3SE260H780C3N Comparaison
Comparaison détaillée côte à côte de EP3SE260H780C3 par Intel et EP3SE260H780C3N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
EP3SE260H780C3N - Stratix III E FPGA, 255K LE, 780-BGA | Intel / Altera
EP3SE260H780C3N ✓ ActifComparaison des spécifications
| Paramètre | EP3SE260H780C3 | EP3SE260H780C3N |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $1 180,00 | $1 325,00 |
| Device Family | Stratix III Enhanced (Stratix III E) | — |
| Series | EP3SE | Stratix® III E |
| Logic Elements | 255,000 | — |
| Logic Array Blocks (LABs) | 10200 | — |
| Embedded Memory | 16,672,768 bits (16.67 Mbit) | — |
| User I/Os | 488 | 488 |
| Operating Voltage (Core) | 0.9 V | — |
| Operating Voltage (Auxiliary) | 1.1 V | — |
| Process Technology | 65 nm CMOS | 40 nm CMOS |
| Speed Grade | C3 | — |
| Température de fonctionnement | Commercial, 0C to +85C | 0 °C to +85 °C (C grade, commercial) |
| Maximum Core Frequency | 500 MHz | [DATA_NEEDED: maximum core frequency MHz] |
| Boîtier | 780-ball FCBGA (HBGA), flip-chip | 780-BBGA, FCBGA (H780) |
| Type de montage | Surface Mount (BGA) | Surface Mount |
| Niveau de sensibilité à l'humidité (MSL) | 3 (168 hours) | [DATA_NEEDED: MSL level per JEDEC J-STD-020] |
| Packaging Type | Tray | — |
| Configuration Memory Support | Fast passive parallel, JTAG, Active Serial | — |
| Statut RoHS | Compliant (per product listings) | Compliant (lead-free 'N' suffix) |
| Logic Elements (LE) | — | 255,000 |
| Embedded Memory (bits) | — | 16,672,768 |
| Number of LABs/CLBs | — | 10,200 |
| Number of Pins / Balls | — | 780 |
| Supply Voltage (VCCINT) | — | [DATA_NEEDED: VCCINT nominal V] |
| Transceivers | — | [DATA_NEEDED: number of embedded transceivers and max data rate] |
| DSP Blocks | — | [DATA_NEEDED: number of DSP blocks and precision] |
| Configuration Method | — | SRAM-based, configured via JTAG / passive / active serial / fast passive parallel |
| Design Toolchain | — | Altera Quartus II (legacy); Intel Quartus Prime |