EP610DC-20 vs EP610ILC-25 Comparación
Comparación detallada lado a lado de EP610DC-20 por Intel y EP610ILC-25 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP610DC-20 | EP610ILC-25 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $15,85 | $9,85 |
| Product Type | CMOS UV-Erasable Programmable Logic Device (EPLD) | — |
| Family | Classic EP610 | Classic EPLD (EP610 series) |
| Logic Macrocells | 16 | — |
| Dedicated Inputs | 4 | 4 |
| I/O Pins | 16 (bidirectional) | — |
| Total Usable Pins | 20 | — |
| Product Terms (p-terms) | 160 | — |
| Propagation Delay (tPD) | 22 ns | — |
| Maximum Toggle Frequency (fMAX) | 55.6 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 4.75 V to 5.25 V |
| Temperatura de funcionamiento | 0 °C to 70 °C (commercial) | — |
| Encapsulado | 24-pin Ceramic DIP (CDIP-24) with UV window | 28-pin PLCC (J-lead) |
| Programming Method | UV erasure + parallel programmer | In-system, electrically erasable |
| Process Technology | CMOS, UV-erasable floating gate | CMOS, electrically erasable |
| Tipo de montaje | Through-hole | Surface Mount |
| Estado RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Device Type | — | EEPLD (Electrically Erasable PLD) |
| Usable Gates | — | 300 |
| Macrocells | — | 16 |
| Product Terms | — | 160 |
| Maximum Operating Frequency (fMAX) | — | 40 MHz |
| Pin-to-Pin Propagation Delay (tPD) | — | 25 ns |
| Nominal Supply Voltage | — | 5 V |
| Total Inputs | — | 20 |
| Bidirectional I/O Pins | — | 16 |
| Rango de temperatura de funcionamiento | — | 0 C to +70 C (commercial) |