EP610DC-20 vs EP610ILC-25 比較
詳細な並列比較: EP610DC-20 メーカー: Intel および EP610ILC-25 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP610DC-20 | EP610ILC-25 |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $15.85 | $9.85 |
| Product Type | CMOS UV-Erasable Programmable Logic Device (EPLD) | — |
| Family | Classic EP610 | Classic EPLD (EP610 series) |
| Logic Macrocells | 16 | — |
| Dedicated Inputs | 4 | 4 |
| I/O Pins | 16 (bidirectional) | — |
| Total Usable Pins | 20 | — |
| Product Terms (p-terms) | 160 | — |
| Propagation Delay (tPD) | 22 ns | — |
| Maximum Toggle Frequency (fMAX) | 55.6 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 4.75 V to 5.25 V |
| 動作温度 | 0 °C to 70 °C (commercial) | — |
| パッケージ | 24-pin Ceramic DIP (CDIP-24) with UV window | 28-pin PLCC (J-lead) |
| Programming Method | UV erasure + parallel programmer | In-system, electrically erasable |
| Process Technology | CMOS, UV-erasable floating gate | CMOS, electrically erasable |
| 実装タイプ | Through-hole | Surface Mount |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Device Type | — | EEPLD (Electrically Erasable PLD) |
| Usable Gates | — | 300 |
| Macrocells | — | 16 |
| Product Terms | — | 160 |
| Maximum Operating Frequency (fMAX) | — | 40 MHz |
| Pin-to-Pin Propagation Delay (tPD) | — | 25 ns |
| Nominal Supply Voltage | — | 5 V |
| Total Inputs | — | 20 |
| Bidirectional I/O Pins | — | 16 |
| 動作温度範囲 | — | 0 C to +70 C (commercial) |