EP910IDI-15 vs EP910DC-35 Comparación
Comparación detallada lado a lado de EP910IDI-15 por Altera y EP910DC-35 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP910IDI-15 | EP910DC-35 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $29,00 | $10,95 |
| Family | Classic EPLD | Classic EPLD EP910 |
| Device Type | CPLD (Complex Programmable Logic Device) | UV-Erasable CMOS PLD (PAL-type) |
| Logic Gates | 450 gates | — |
| Macrocells | 24 | 24 |
| Maximum User I/O Pins | 36 | — |
| Pin-to-Pin Propagation Delay (tpd) | 15 ns | — |
| Maximum Counter Frequency | 66.6 MHz | — |
| Supply Voltage (Vcc) | 5 V | 4.75 V to 5.25 V (5 V nominal) |
| Technology | CMOS EPROM | CMOS, UV-erasable EPROM cell |
| Program/Erase Method | UV-erasable windowed CerDIP | — |
| Encapsulado | 40-pin CDIP (CerDIP) with quartz window | 40-pin CDIP (Ceramic DIP) with quartz window |
| Temperatura de funcionamiento | -40C to +85C (industrial, "I" grade) | 0 °C to +70 °C (commercial) |
| Tipo de montaje | Through-hole (DIP) | — |
| Macrocells Configurable As | D, T, JK, SR flip-flop, or combinatorial | — |
| Development Tool | MAX+PLUS II (legacy) / Altera Classic compiler | — |
| Programming Hardware | Altera Logic Programmer card | — |
| Estado RoHS | [DATA_NEEDED: RoHS compliance of CDIP windowed part] | Non-compliant (ceramic DIP with Pb-bearing lead finish) |
| Logic Family Compatibility | Pin-, function-, and JEDEC-map compatible across all EP910 speed grades and packages | — |
| Architecture | — | PAL-type sum-of-products AND-OR array |
| Usable Gates | — | 900 gates |
| Product Terms | — | 240 |
| Dedicated Inputs | — | 12 |
| I/O Pins | — | 24 |
| Total Inputs | — | 36 |
| Propagation Delay (tpd) | — | 35 ns |
| Frecuencia de reloj máxima | — | 37 MHz (typical, internal) |
| Lead Pitch | — | 2.540 mm |
| Termination Style | — | Through-Hole |
| Programming Method | — | JEDEC fuse map via device programmer; UV erase |
| Lifecycle | — | Obsolete / last-time-buy from authorized distributors |