EP910IDI-15 vs EP910DC-35 Comparaison
Comparaison détaillée côte à côte de EP910IDI-15 par Altera et EP910DC-35 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP910IDI-15 | EP910DC-35 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $29,00 | $10,95 |
| Family | Classic EPLD | Classic EPLD EP910 |
| Device Type | CPLD (Complex Programmable Logic Device) | UV-Erasable CMOS PLD (PAL-type) |
| Logic Gates | 450 gates | — |
| Macrocells | 24 | 24 |
| Maximum User I/O Pins | 36 | — |
| Pin-to-Pin Propagation Delay (tpd) | 15 ns | — |
| Maximum Counter Frequency | 66.6 MHz | — |
| Supply Voltage (Vcc) | 5 V | 4.75 V to 5.25 V (5 V nominal) |
| Technology | CMOS EPROM | CMOS, UV-erasable EPROM cell |
| Program/Erase Method | UV-erasable windowed CerDIP | — |
| Boîtier | 40-pin CDIP (CerDIP) with quartz window | 40-pin CDIP (Ceramic DIP) with quartz window |
| Température de fonctionnement | -40C to +85C (industrial, "I" grade) | 0 °C to +70 °C (commercial) |
| Type de montage | Through-hole (DIP) | — |
| Macrocells Configurable As | D, T, JK, SR flip-flop, or combinatorial | — |
| Development Tool | MAX+PLUS II (legacy) / Altera Classic compiler | — |
| Programming Hardware | Altera Logic Programmer card | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance of CDIP windowed part] | Non-compliant (ceramic DIP with Pb-bearing lead finish) |
| Logic Family Compatibility | Pin-, function-, and JEDEC-map compatible across all EP910 speed grades and packages | — |
| Architecture | — | PAL-type sum-of-products AND-OR array |
| Usable Gates | — | 900 gates |
| Product Terms | — | 240 |
| Dedicated Inputs | — | 12 |
| I/O Pins | — | 24 |
| Total Inputs | — | 36 |
| Propagation Delay (tpd) | — | 35 ns |
| Fréquence d'horloge maximale | — | 37 MHz (typical, internal) |
| Lead Pitch | — | 2.540 mm |
| Termination Style | — | Through-Hole |
| Programming Method | — | JEDEC fuse map via device programmer; UV erase |
| Lifecycle | — | Obsolete / last-time-buy from authorized distributors |