EP910IDI-15 vs EP910DC-35 比較

詳細な並列比較: EP910IDI-15 メーカー: Altera および EP910DC-35 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。

仕様比較

パラメータ EP910IDI-15 EP910DC-35
ブランド Altera Altera
カテゴリ FPGA & CPLD FPGA & CPLD
ライフサイクル状態 Obsolete Obsolete
在庫状況 In Stock In Stock
単価(USD) $29.00 $10.95
Family Classic EPLD Classic EPLD EP910
Device Type CPLD (Complex Programmable Logic Device) UV-Erasable CMOS PLD (PAL-type)
Logic Gates 450 gates —
Macrocells 24 24
Maximum User I/O Pins 36 —
Pin-to-Pin Propagation Delay (tpd) 15 ns —
Maximum Counter Frequency 66.6 MHz —
Supply Voltage (Vcc) 5 V 4.75 V to 5.25 V (5 V nominal)
Technology CMOS EPROM CMOS, UV-erasable EPROM cell
Program/Erase Method UV-erasable windowed CerDIP —
パッケージ 40-pin CDIP (CerDIP) with quartz window 40-pin CDIP (Ceramic DIP) with quartz window
動作温度 -40C to +85C (industrial, "I" grade) 0 °C to +70 °C (commercial)
実装タイプ Through-hole (DIP) —
Macrocells Configurable As D, T, JK, SR flip-flop, or combinatorial —
Development Tool MAX+PLUS II (legacy) / Altera Classic compiler —
Programming Hardware Altera Logic Programmer card —
RoHS ステータス [DATA_NEEDED: RoHS compliance of CDIP windowed part] Non-compliant (ceramic DIP with Pb-bearing lead finish)
Logic Family Compatibility Pin-, function-, and JEDEC-map compatible across all EP910 speed grades and packages —
Architecture — PAL-type sum-of-products AND-OR array
Usable Gates — 900 gates
Product Terms — 240
Dedicated Inputs — 12
I/O Pins — 24
Total Inputs — 36
Propagation Delay (tpd) — 35 ns
最大クロック周波数 — 37 MHz (typical, internal)
Lead Pitch — 2.540 mm
Termination Style — Through-Hole
Programming Method — JEDEC fuse map via device programmer; UV erase
Lifecycle — Obsolete / last-time-buy from authorized distributors

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