EP910LC-35T vs EP910LC-35H Comparación
Comparación detallada lado a lado de EP910LC-35T por Altera y EP910LC-35H por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP910LC-35T | EP910LC-35H |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $28,90 | $25,00 |
| Family | Classic EPLD (EP910) | Classic EPLD (EP910) |
| Logic Capacity | 450 usable gates | — |
| Macrocells | 24 | — |
| Propagation Delay (tPD) | 35 ns | — |
| Maximum Operating Frequency | 28.6 MHz | — |
| Supply Voltage (VCC) | 5 V | 5 V (4.75 V to 5.25 V) |
| User I/O Pins | 36 | 36 |
| Encapsulado | PLCC-44 (J-lead) | 40-pin Ceramic DIP (H suffix) |
| Process Technology | CMOS (EPROM-based) | — |
| Temperatura de funcionamiento | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range grade] |
| Erasure Method | UV-erasable window (ceramic package) / OTP (plastic) | UV (quartz window on H package) |
| Programming | Altera programming hardware + MAX+PLUS II | — |
| Tipo de montaje | Surface Mount (PLCC socket or solder) | Through-hole (Ceramic DIP) |
| Nivel MSL | MSL 3 (168 hours) | — |
| Estado RoHS | [DATA_NEEDED: RoHS status not in verified data] | unknown |
| Logic Elements | — | 24 macrocells |
| Equivalent Gates | — | 450 usable gates |
| Propagation Delay (tpd) | — | 35 ns |
| Technology | — | CMOS, UV-erasable EPROM |
| Dedicated Inputs | — | 10 |
| Programming Method | — | Altera hardware programmer |
| Logic Levels | — | TTL compatible |
| Corriente en reposo | — | [DATA_NEEDED: typical ICC value] |
| Process Node | — | [DATA_NEEDED: process geometry] |
| Lifecycle | — | Obsolete (long-term supply via Rochester Electronics) |