EP910LC-35T vs EP910LC-35H 비교
다음의 상세 나란히 비교: EP910LC-35T 제조: Altera 및 EP910LC-35H 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EP910LC-35T | EP910LC-35H |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | NRND | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $28.90 | $25.00 |
| Family | Classic EPLD (EP910) | Classic EPLD (EP910) |
| Logic Capacity | 450 usable gates | — |
| Macrocells | 24 | — |
| Propagation Delay (tPD) | 35 ns | — |
| Maximum Operating Frequency | 28.6 MHz | — |
| Supply Voltage (VCC) | 5 V | 5 V (4.75 V to 5.25 V) |
| User I/O Pins | 36 | 36 |
| 패키지 | PLCC-44 (J-lead) | 40-pin Ceramic DIP (H suffix) |
| Process Technology | CMOS (EPROM-based) | — |
| 동작 온도 | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range grade] |
| Erasure Method | UV-erasable window (ceramic package) / OTP (plastic) | UV (quartz window on H package) |
| Programming | Altera programming hardware + MAX+PLUS II | — |
| 실장 유형 | Surface Mount (PLCC socket or solder) | Through-hole (Ceramic DIP) |
| MSL 레벨 | MSL 3 (168 hours) | — |
| RoHS 상태 | [DATA_NEEDED: RoHS status not in verified data] | unknown |
| Logic Elements | — | 24 macrocells |
| Equivalent Gates | — | 450 usable gates |
| Propagation Delay (tpd) | — | 35 ns |
| Technology | — | CMOS, UV-erasable EPROM |
| Dedicated Inputs | — | 10 |
| Programming Method | — | Altera hardware programmer |
| Logic Levels | — | TTL compatible |
| 대기 전류 | — | [DATA_NEEDED: typical ICC value] |
| Process Node | — | [DATA_NEEDED: process geometry] |
| Lifecycle | — | Obsolete (long-term supply via Rochester Electronics) |