EP910LI-20 vs EP910LI-50 Comparación
Comparación detallada lado a lado de EP910LI-20 por Altera y EP910LI-50 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP910LI-20 | EP910LI-50 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $19,95 | $65,00 |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Macrocells | 24 | 24 |
| Maximum Operating Frequency | 62 MHz | — |
| Propagation Delay (tpd) | 20 ns | — |
| Dedicated Inputs | 16 | — |
| I/O Pins | 24 | [DATA_NEEDED: I/O pin count] |
| Supply Voltage (VCC) | 5 V | 5 V +/- 10% |
| Temperatura de funcionamiento | -40C to +85C (Industrial) | -40C to +85C (industrial) |
| Encapsulado | 40-pin Ceramic DIP (Windowed) | — |
| Technology | CMOS, UV-erasable | CMOS, UV-erasable EPROM |
| Package Type | Through-Hole, Ceramic DIP with Quartz Window | CERDIP-40 (L) |
| Temperature Grade | Industrial (-40C to +85C) | — |
| Recuento de pines | 40 | — |
| Logic Family | EPLD (Erasable PLD) | — |
| Architecture | Sum-of-products macrocell | — |
| Pin/Package Compatibility | Pin-compatible across EP910 family | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Usable Gates | — | 450 |
| Propagation Delay (tPD) | — | 50 ns |
| Package Pin Count | — | 40 |
| Logic Blocks | — | Classic AND/OR array architecture |
| Programming Method | — | EPROM programmer (UV-erasable window) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Speed Grade Suffix | — | -50 (50 ns tPD) |