EP910LI-40T vs EP910LC-40T Comparación
Comparación detallada lado a lado de EP910LI-40T por Intel y EP910LC-40T por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP910LI-40T | EP910LC-40T |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,75 | $10,40 |
| Family | Classic EPLD | Altera Classic EPLD |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | — |
| I/O Pins | 24 | — |
| Maximum Inputs | 36 | — |
| Maximum Outputs | 24 | — |
| Product Terms | 240 | — |
| Propagation Delay (tPD) | 40 ns | 40 ns |
| Technology | CMOS, UV-erasable EPROM | CMOS, UV-erasable |
| Tensión de alimentación | 5 V (typical) | 5 V (4.75 V to 5.25 V) |
| Temperatura de funcionamiento | -40C to +85C (Industrial) | -40 C to +85 C (commercial, per -LC suffix family) |
| Architecture | PAL-type with global bus | — |
| Encapsulado | Tape and Reel (suffix T); 40-pin DIP / 44-pin PLCC | PLCC-44 (PQCC44) |
| Estado RoHS | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS status - not stated in web data] |
| Programming Method | Altera Master Programming Unit (MPU), no JTAG | — |
| Equivalent Gates | — | 450 gates |
| Logic Array Blocks | — | 4 Logic Expandable AND-OR arrays |
| User I/O Pins | — | 36 |
| Maximum Frequency (fMAX) | — | 25 MHz |
| Programming | — | Altera MAX+PLUS II / APLUS tools |
| Erase/Reprogram Cycles | — | 100 (windowed UV-erase family) |
| Recuento de pines | — | 44 |
| Packaging Option | — | Tape and Reel (T suffix) |