EP910LI-40T vs EP910LC-40T 比較
詳細な並列比較: EP910LI-40T メーカー: Intel および EP910LC-40T メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP910LI-40T | EP910LC-40T |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $9.75 | $10.40 |
| Family | Classic EPLD | Altera Classic EPLD |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | — |
| I/O Pins | 24 | — |
| Maximum Inputs | 36 | — |
| Maximum Outputs | 24 | — |
| Product Terms | 240 | — |
| Propagation Delay (tPD) | 40 ns | 40 ns |
| Technology | CMOS, UV-erasable EPROM | CMOS, UV-erasable |
| 電源電圧 | 5 V (typical) | 5 V (4.75 V to 5.25 V) |
| 動作温度 | -40C to +85C (Industrial) | -40 C to +85 C (commercial, per -LC suffix family) |
| Architecture | PAL-type with global bus | — |
| パッケージ | Tape and Reel (suffix T); 40-pin DIP / 44-pin PLCC | PLCC-44 (PQCC44) |
| RoHS ステータス | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS status - not stated in web data] |
| Programming Method | Altera Master Programming Unit (MPU), no JTAG | — |
| Equivalent Gates | — | 450 gates |
| Logic Array Blocks | — | 4 Logic Expandable AND-OR arrays |
| User I/O Pins | — | 36 |
| Maximum Frequency (fMAX) | — | 25 MHz |
| Programming | — | Altera MAX+PLUS II / APLUS tools |
| Erase/Reprogram Cycles | — | 100 (windowed UV-erase family) |
| ピン数 | — | 44 |
| Packaging Option | — | Tape and Reel (T suffix) |