EP910PC-25 vs EP910PC-15 Comparación
Comparación detallada lado a lado de EP910PC-25 por Altera y EP910PC-15 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP910PC-25 | EP910PC-15 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $16,92 | $12,80 |
| Product Family | Classic EPLD | — |
| Usable Gates | 900 | 900 |
| Integration Gates (typical) | 4800 | — |
| Macrocells | 24 | 24 |
| Pin-to-Pin Delay (tPD) | 25 ns | — |
| Maximum Operating Frequency (fMAX) | 33.3 MHz | — |
| Supply Voltage (VCC) | 5 V +/- 10% | 4.75 V to 5.25 V (5 V nominal) |
| Technology | CMOS EPROM | — |
| Encapsulado | PDIP-24 (Plastic DIP) | 24-pin PDIP (PDIP-24, 0.300 inch) |
| Recuento de pines | 24 | — |
| Dedicated Inputs | 10 | 10 |
| Dedicated I/O Pins | 12 | 12 |
| TTL Compatibility | 100% TTL emulation | — |
| Temperatura de funcionamiento | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Erasure Method | Not erasable in plastic package (windowless) | — |
| Family | — | Altera Classic EPLD |
| Maximum Pin-to-Pin Delay (tpd) | — | 15 ns |
| Counter Frequency (fCNT) | — | 100 MHz |
| Supply Current (Icc) | — | 80 mA typical |
| Tipo de montaje | — | Through-Hole |
| Process Technology | — | CMOS, UV-erasable |
| Programming Method | — | Altera Logic Programmer card |
| Estado RoHS | — | [DATA_NEEDED: RoHS status - EP910 is a legacy through-hole part, likely non-RoHS] |
| Nivel MSL | — | Not applicable (through-hole) |