EP910PC-25 vs EP910PC-15 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910PC-25 sa pamamagitan ng Altera at EP910PC-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910PC-25 | EP910PC-15 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Product Family | Classic EPLD | — |
| Usable Gates | 900 | 900 |
| Integration Gates (typical) | 4800 | — |
| Macrocells | 24 | 24 |
| Pin-to-Pin Delay (tPD) | 25 ns | — |
| Maximum Operating Frequency (fMAX) | 33.3 MHz | — |
| Supply Voltage (VCC) | 5 V +/- 10% | 4.75 V to 5.25 V (5 V nominal) |
| Technology | CMOS EPROM | — |
| Packhaging | PDIP-24 (Plastic DIP) | 24-pin PDIP (PDIP-24, 0.300 inch) |
| Bilang ng Pin | 24 | — |
| Dedicated Inputs | 10 | 10 |
| Dedicated I/O Pins | 12 | 12 |
| TTL Compatibility | 100% TTL emulation | — |
| Temperature na Operasyon | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Erasure Method | Not erasable in plastic package (windowless) | — |
| Family | — | Altera Classic EPLD |
| Maximum Pin-to-Pin Delay (tpd) | — | 15 ns |
| Counter Frequency (fCNT) | — | 100 MHz |
| Supply Current (Icc) | — | 80 mA typical |
| Uri ng Pagpapasok | — | Through-Hole |
| Process Technology | — | CMOS, UV-erasable |
| Programming Method | — | Altera Logic Programmer card |
| Tindminan RoHS | — | [DATA_NEEDED: RoHS status - EP910 is a legacy through-hole part, likely non-RoHS] |
| Level ng MSL | — | Not applicable (through-hole) |