EP910PI-20T vs EP910PI-12T Comparación
Comparación detallada lado a lado de EP910PI-20T por Intel y EP910PI-12T por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP910PI-20T | EP910PI-12T |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,95 | $9,95 |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Device | EP910 | — |
| Number of Macrocells | 24 | — |
| Number of Usable Gates | [DATA_NEEDED: usable gate count] | — |
| Propagation Delay (tpd) | 20 ns | — |
| Maximum Toggle Frequency | 62.5 MHz | — |
| Number of Dedicated Inputs | 12 | — |
| Number of I/O Pins | 20 | — |
| Número de pines | 40 | — |
| Encapsulado | PDIP-40 (PI) | 40-pin PDIP (Plastic DIP) |
| Tipo de montaje | Through-Hole (DIP) | — |
| Technology | CMOS EPROM (UV-erasable) | — |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| Programming | Standard EPROM programmer, JEDEC map | — |
| Estado RoHS | unknown | Non-compliant (legacy PDIP package, contains lead) |
| Estado del ciclo de vida | Not Recommended for New Designs (NRND) | NRND / EOL (mature legacy product) |
| Macrocells | — | 24 |
| Propagation Delay (tPD) | — | 12 ns |
| Maximum Operating Frequency | — | 76.9 MHz |
| Logic Gates | — | [DATA_NEEDED: logic gate count] |
| Supply Voltage (VCC) | — | 5 V (4.75 V min, 5.25 V max) |
| I/O Pins | — | 24 |
| Dedicated Inputs | — | 12 |
| External Clock Inputs | — | 2 |
| Outputs | — | 24 |
| Terminals / Pin Count | — | 44 (PDIP-40 package pinout with NC pins) |
| Process Technology | — | CMOS |
| Programmable Technology | — | UV-erasable EPROM |
| Programming Interface | — | JEDEC-standard |