EP910PI-20T vs EP910PI-12T Comparison

Detailed side-by-side comparison of EP910PI-20T by Intel and EP910PI-12T by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP910PI-20T EP910PI-12T
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $9.95 $9.95
Family Altera Classic EPLD Altera Classic EPLD
Device EP910 β€”
Number of Macrocells 24 β€”
Number of Usable Gates [DATA_NEEDED: usable gate count] β€”
Propagation Delay (tpd) 20 ns β€”
Maximum Toggle Frequency 62.5 MHz β€”
Number of Dedicated Inputs 12 β€”
Number of I/O Pins 20 β€”
Number of Pins 40 β€”
Package PDIP-40 (PI) 40-pin PDIP (Plastic DIP)
Mounting Type Through-Hole (DIP) β€”
Technology CMOS EPROM (UV-erasable) β€”
Operating Temperature [DATA_NEEDED: operating temperature range] 0C to +70C (commercial)
Programming Standard EPROM programmer, JEDEC map β€”
RoHS Status unknown Non-compliant (legacy PDIP package, contains lead)
Lifecycle Status Not Recommended for New Designs (NRND) NRND / EOL (mature legacy product)
Macrocells β€” 24
Propagation Delay (tPD) β€” 12 ns
Maximum Operating Frequency β€” 76.9 MHz
Logic Gates β€” [DATA_NEEDED: logic gate count]
Supply Voltage (VCC) β€” 5 V (4.75 V min, 5.25 V max)
I/O Pins β€” 24
Dedicated Inputs β€” 12
External Clock Inputs β€” 2
Outputs β€” 24
Terminals / Pin Count β€” 44 (PDIP-40 package pinout with NC pins)
Process Technology β€” CMOS
Programmable Technology β€” UV-erasable EPROM
Programming Interface β€” JEDEC-standard

Datasheets & Resources

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