EP910PI-40 vs EP910PC-20 Comparación
Comparación detallada lado a lado de EP910PI-40 por Altera y EP910PC-20 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP910PI-40 | EP910PC-20 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Última compra | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,85 | $12,40 |
| Device Family | Classic EPLD | — |
| Part Number | EP910PI-40 | — |
| Architecture | PAL-type macrocell, CMOS, UV-erasable | — |
| Number of Macrocells | 24 | — |
| Number of Dedicated Inputs | 12 | — |
| Number of I/O Lines | 24 | — |
| External Clock Inputs | 2 | — |
| Frecuencia de reloj máxima | 25 MHz | — |
| Propagation Delay (tPD) | 43 ns | — |
| Speed Grade | -40 (43 ns) | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V |
| Encapsulado | PDIP-40 (Plastic DIP, 40-pin) | PDIP-24 (PC suffix) |
| Temperatura de funcionamiento | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Tipo de montaje | Through-Hole | Through-Hole (DIP) |
| Process Technology | CMOS (UV-erasable) | — |
| Estado RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Programming Method | UV-erase + Altera programmer (legacy) | EPROM programmer, JEDEC fuse map |
| Programmable Polarity | Yes (user-configurable output) | — |
| Output Enable Control | Yes (per-pin three-state) | — |
| Family | — | Altera Classic EPLD |
| Device | — | EP910 |
| Usable Gates | — | 900 |
| Macrocell Count | — | [DATA_NEEDED: macrocell count] |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| Recuento de pines | — | 24 |
| Technology | — | CMOS EPROM (UV-erasable) |
| I/O Compatibility | — | 100% TTL |
| Nivel MSL | — | [DATA_NEEDED: MSL level] |