EP910PI-40 vs EP910PC-20 Vergleich
Detaillierter Direktvergleich von EP910PI-40 von Altera und EP910PC-20 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EP910PI-40 - 24-Macrocell Classic EPLD, 43ns, PDIP-40 | Altera
EP910PI-40 ⚠ Letzte Bestellmöglichkeit
Spezifikationsvergleich
| Parameter | EP910PI-40 | EP910PC-20 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,85 | $12,40 |
| Device Family | Classic EPLD | — |
| Part Number | EP910PI-40 | — |
| Architecture | PAL-type macrocell, CMOS, UV-erasable | — |
| Number of Macrocells | 24 | — |
| Number of Dedicated Inputs | 12 | — |
| Number of I/O Lines | 24 | — |
| External Clock Inputs | 2 | — |
| Maximale Taktfrequenz | 25 MHz | — |
| Propagation Delay (tPD) | 43 ns | — |
| Speed Grade | -40 (43 ns) | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V |
| Gehäuse | PDIP-40 (Plastic DIP, 40-pin) | PDIP-24 (PC suffix) |
| Betriebstemperatur | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Montageart | Through-Hole | Through-Hole (DIP) |
| Process Technology | CMOS (UV-erasable) | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Programming Method | UV-erase + Altera programmer (legacy) | EPROM programmer, JEDEC fuse map |
| Programmable Polarity | Yes (user-configurable output) | — |
| Output Enable Control | Yes (per-pin three-state) | — |
| Family | — | Altera Classic EPLD |
| Device | — | EP910 |
| Usable Gates | — | 900 |
| Macrocell Count | — | [DATA_NEEDED: macrocell count] |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| Pin-Anzahl | — | 24 |
| Technology | — | CMOS EPROM (UV-erasable) |
| I/O Compatibility | — | 100% TTL |
| MSL-Level | — | [DATA_NEEDED: MSL level] |