EP910PI-40 vs EP910PC-20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910PI-40 sa pamamagitan ng Altera at EP910PC-20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910PI-40 | EP910PC-20 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Obsolete |
| Device Family | Classic EPLD | — |
| Part Number | EP910PI-40 | — |
| Architecture | PAL-type macrocell, CMOS, UV-erasable | — |
| Number of Macrocells | 24 | — |
| Number of Dedicated Inputs | 12 | — |
| Number of I/O Lines | 24 | — |
| External Clock Inputs | 2 | — |
| Maksimum na Taktiko ng Oras | 25 MHz | — |
| Propagation Delay (tPD) | 43 ns | — |
| Speed Grade | -40 (43 ns) | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V |
| Packhaging | PDIP-40 (Plastic DIP, 40-pin) | PDIP-24 (PC suffix) |
| Temperature na Operasyon | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Uri ng Pagpapasok | Through-Hole | Through-Hole (DIP) |
| Process Technology | CMOS (UV-erasable) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Programming Method | UV-erase + Altera programmer (legacy) | EPROM programmer, JEDEC fuse map |
| Programmable Polarity | Yes (user-configurable output) | — |
| Output Enable Control | Yes (per-pin three-state) | — |
| Family | — | Altera Classic EPLD |
| Device | — | EP910 |
| Usable Gates | — | 900 |
| Macrocell Count | — | [DATA_NEEDED: macrocell count] |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| Bilang ng Pin | — | 24 |
| Technology | — | CMOS EPROM (UV-erasable) |
| I/O Compatibility | — | 100% TTL |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |