EPC1LI20 vs EPC2LC20 Comparación
Comparación detallada lado a lado de EPC1LI20 por Altera y EPC2LC20 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPC1LI20 | EPC2LC20 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | Memory ICs | Memory ICs |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $8,50 | $7,20 |
| Tipo de memoria | OTP Configuration PROM (EPROM-based) | Non-volatile configuration PROM |
| Tamaño de memoria | 1 Mb (1,048,576 bits) | 1.6 Mbit |
| Configuration Interface | Altera Passive Serial / Altera Active Serial / JTAG (IEEE 1149.1) | Serial (x1) to FPGA via DCLK/nCONFIG/nSTATUS/CONF_DONE |
| Maximum Configuration Clock | 8 MHz | — |
| Supply Voltage (VCC) | 5.0 V (4.75 V to 5.25 V) | — |
| Programming Voltage (VPP) | 12.75 V (typical, factory-programmed via JTAG) | — |
| Encapsulado | 20-pin PLCC (J-lead, 9x9 mm) | 20-pin PLCC (J-lead, 9x9 mm) |
| Recuento de pines | 20 | — |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | -40C to +85C (industrial) [DATA_NEEDED: exact grade from datasheet] |
| Cascading Support | Yes (nCASC pin for multi-device daisy chain) | — |
| Endurance | OTP (one-time programmable, 1000 erase-equivalent UV cycles for pre-program erase) | — |
| JTAG Programming | Yes (in-system via IEEE 1149.1) | — |
| Compatible FPGA Families | FLEX 8000, FLEX 10K, ACEX 1K, APEX 20K, Mercury | — |
| Tipo de montaje | Surface Mount (PLCC socket compatible) | Surface Mount |
| Nivel MSL | 1 (per Partstack datasheet record) | — |
| Estado RoHS | [DATA_NEEDED: RoHS status - original Altera part may be non-RoHS SnPb finish] | Non-Compliant (original Altera Pb-containing part) |
| Programming Interface | — | IEEE 1149.1 (JTAG) ISP, 5.0-V and 3.3-V tolerant |
| Supply Voltage VCC | — | 3.0 V to 3.6 V (3.3-V operation) |
| ISP Voltage Range | — | 5.0 V or 3.3 V |
| Supported FPGA Families | — | ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, MAX 9000 |
| Cascade Support | — | Yes - daisy-chain multiple EPC2 devices via JTAG for larger bitstreams |
| Lead-Free Version | — | EPC2LC20N available as lead-free equivalent |
| Programming Support | — | Altera Programming Unit (APU), Quartus II, JTAG programmer |
| Boundary-Scan | — | IEEE 1149.1 compliant, 8-bit or 16-bit JTAG |