EPC2C20 vs EPC2LC20CAD Comparación
Comparación detallada lado a lado de EPC2C20 por Altera y EPC2LC20CAD por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPC2C20 | EPC2LC20CAD |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | Memory ICs |
| Estado del ciclo de vida | Activo | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $0,00 | $9,75 |
| Manufacturer | Altera | — |
| MPN | EPC2C20 | — |
| Device Type | Configuration device integrated circuit | — |
| Primary Function | Configuration of SRAM-based lookup-table devices | — |
| Configuration Architecture | Single-device configuration solution | — |
| Architecture Block 1 | Configuration controller | — |
| Architecture Block 2 | Flash memory | — |
| Memory Technology | Flash memory | — |
| Supported Device Class | SRAM-based LUT devices | — |
| Configuration Mode | [DATA_NEEDED: configuration mode] | Serial (bit-wide, Altera FPGAs) |
| Memory Density | [DATA_NEEDED: memory density] | — |
| Configuration Data Interface | [DATA_NEEDED: configuration data interface] | — |
| Operating Voltage | [DATA_NEEDED: operating voltage] | — |
| Configuration Clock Frequency | [DATA_NEEDED: configuration clock frequency] | — |
| Encapsulado | [DATA_NEEDED: package] | 20-pin J-lead PLCC (PLCC-20) |
| Recuento de pines | [DATA_NEEDED: pin count] | 20 |
| Rango de temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | Compliant |
| REACH Status | [DATA_NEEDED: REACH status] | — |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification] | — |
| Tipo de memoria | — | Configuration PROM (Flash) |
| Memory Capacity | — | 1.6 Mbit |
| Tensión de alimentación | — | 3.3 V (nominal) |
| I/O Voltage Tolerance | — | 5 V tolerant |
| Program Interface | — | IEEE Std 1149.1 JTAG (in-system programmable) |
| Temperatura de funcionamiento | — | -40C to +85C (commercial) |
| Maximum Input Voltage (DC) | — | -0.3 V to +7.0 V |
| Input Undershoot/Overshoot | — | -2.0 V to +7.0 V for <100 mA, <20 ns no-load |
| Compatible FPGA Families | — | APEX 20K, ACEX 1K, Cyclone, Stratix |
| Programming Method | — | JTAG ISP (no external programmer required) |
| Tipo de montaje | — | Surface Mount / Through-hole (PLCC socket) |