EPC2LI20J vs EPC2LI20 Comparación
Comparación detallada lado a lado de EPC2LI20J por Altera y EPC2LI20 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPC2LI20J | EPC2LI20 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | Memory ICs | Memory ICs |
| Estado del ciclo de vida | Activo | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,75 | $5,95 |
| Tipo de memoria | In-System Programmable Configuration PROM (flash) | Flash (in-system programmable) |
| Tamaño de memoria | 1,695,680 bits (1.6Mb) | 1.6 Mb (1,572,864 bits) |
| Organización de memoria | 65,536 x 1-bit (serial interface) | — |
| Interfaz | Altera 4-pin serial configuration (DATA, DCLK, nCS, nCONFIG) | — |
| Target FPGAs | APEX II, APEX 20K/20KC/20KE, Mercury, ACEX 1K, FLEX 6000/10KE/10KA | — |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V (3.3 V typical) | — |
| I/O Voltage (VCCIO) | 5.0 V or 3.3 V tolerant | — |
| ISP Programming Interface | JTAG (IEEE 1149.1) | — |
| Cascade Support | Yes (multi-device configuration chain) | — |
| Internal Oscillator | Yes (configures without external clock source) | — |
| Encapsulado | 20-pin PLCC with J-leads (JEDEC MS-018) | — |
| Temperatura de funcionamiento | -40C to +85C (industrial) | -40 C to +85 C (Industrial) |
| Programming Cycles | [DATA_NEEDED: minimum endurance cycles] | — |
| Estado RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Configuration Clock (DCLK) | Up to 33 MHz | — |
| Programmable Type | — | In System Programmable (ISP) |
| Función | — | Configuration PROM for SRAM-based FPGAs |
| Supply Voltage - Operating | — | 3.0 V to 3.6 V and 4.5 V to 5.5 V (auto-sensing) |
| Encapsulado / Carcasa | — | 20-PLCC (J-lead, 9x9 mm) |
| Tipo de montaje | — | Surface Mount (PLCC socket-compatible) |
| Configuration Interface | — | Serial or Byte-wide (parallel) |
| Decompression | — | On-chip (supports compressed bitstreams) |
| JTAG / ISP Interface | — | IEEE 1532 (TCK, TMS, TDI, TDO) |
| Multi-Device Support | — | Yes (daisy-chain configuration) |
| User-Accessible Memory | — | Yes (unused flash available to user logic) |
| Nivel MSL | — | [DATA_NEEDED: MSL level] |