EPC2LI20J vs EPC2LI20 Comparaison
Comparaison détaillée côte à côte de EPC2LI20J par Altera et EPC2LI20 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPC2LI20J | EPC2LI20 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | Memory ICs | Memory ICs |
| Statut du cycle de vie | Actif | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $9,75 | $5,95 |
| Type de mémoire | In-System Programmable Configuration PROM (flash) | Flash (in-system programmable) |
| Taille de mémoire | 1,695,680 bits (1.6Mb) | 1.6 Mb (1,572,864 bits) |
| Organisation de la mémoire | 65,536 x 1-bit (serial interface) | — |
| Interface | Altera 4-pin serial configuration (DATA, DCLK, nCS, nCONFIG) | — |
| Target FPGAs | APEX II, APEX 20K/20KC/20KE, Mercury, ACEX 1K, FLEX 6000/10KE/10KA | — |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V (3.3 V typical) | — |
| I/O Voltage (VCCIO) | 5.0 V or 3.3 V tolerant | — |
| ISP Programming Interface | JTAG (IEEE 1149.1) | — |
| Cascade Support | Yes (multi-device configuration chain) | — |
| Internal Oscillator | Yes (configures without external clock source) | — |
| Boîtier | 20-pin PLCC with J-leads (JEDEC MS-018) | — |
| Température de fonctionnement | -40C to +85C (industrial) | -40 C to +85 C (Industrial) |
| Programming Cycles | [DATA_NEEDED: minimum endurance cycles] | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Configuration Clock (DCLK) | Up to 33 MHz | — |
| Programmable Type | — | In System Programmable (ISP) |
| Fonction | — | Configuration PROM for SRAM-based FPGAs |
| Supply Voltage - Operating | — | 3.0 V to 3.6 V and 4.5 V to 5.5 V (auto-sensing) |
| Boîtier / Format | — | 20-PLCC (J-lead, 9x9 mm) |
| Type de montage | — | Surface Mount (PLCC socket-compatible) |
| Configuration Interface | — | Serial or Byte-wide (parallel) |
| Decompression | — | On-chip (supports compressed bitstreams) |
| JTAG / ISP Interface | — | IEEE 1532 (TCK, TMS, TDI, TDO) |
| Multi-Device Support | — | Yes (daisy-chain configuration) |
| User-Accessible Memory | — | Yes (unused flash available to user logic) |
| Niveau MSL | — | [DATA_NEEDED: MSL level] |