EPF10K200EBC600-2 vs EPF10K250EBC600-3 Comparación
Comparación detallada lado a lado de EPF10K200EBC600-2 por Intel y EPF10K250EBC600-3 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPF10K200EBC600-2 | EPF10K250EBC600-3 |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $198,00 | $205,00 |
| Series | FLEX-10KE | — |
| Logic Family | CMOS (SRAM-based) | — |
| Process Technology | 0.30 µm CMOS | SRAM-based CMOS |
| Typical Gate Count | 200,000 gates | — |
| Logic Elements (LEs) | 9984 | — |
| Logic Array Blocks (LABs) | 1248 | — |
| Embedded Memory (EAB) | 98304 bits (96 Kbits) | — |
| Maximum User I/O | 470 pins | 470 |
| Propagation Delay | 0.4 ns | — |
| Tensión de alimentación | 2.3 V to 2.7 V (core), 2.5/3.3 V (I/O) | — |
| I/O Standards | LVTTL, LVCMOS, PCI, GTL+ | — |
| Package Type | 600-ball BGA (BGA-600) | — |
| Package Dimensions | 45 × 45 mm | — |
| Ball Pitch | 1.27 mm | — |
| Package Height | 1.1 mm max | — |
| Temperatura de funcionamiento | 0°C to +70°C (Commercial) | [DATA_NEEDED: operating temperature range] |
| Tipo de montaje | Surface Mount | — |
| Configuration Method | JTAG (IEEE 1149.1), EPC2 serial PROM | — |
| Part Status | Obsolete | — |
| Estado RoHS | unknown | — |
| Family | — | FLEX 10KE |
| Logic Elements | — | 12,160 LEs |
| Typical Gates | — | 250,000 |
| Embedded Array Blocks (EABs) | — | 12 (each 2 Kbits) |
| Total Embedded Memory | — | 24 Kbits (RAM) |
| PLLs (Phase-Locked Loops) | — | 4 |
| Dedicated Clock Inputs | — | 6 |
| Speed Grade | — | -3 |
| Core Supply Voltage | — | 3.3 V |
| I/O Supply Voltage | — | 3.3 V (5 V tolerant) |
| Encapsulado | — | 600-ball FineLine BGA |
| Configuration Mode | — | Passive Serial / Passive Parallel / JTAG |
| Boundary Scan | — | IEEE 1149.1 (JTAG) |