EPF10K200EBC600-2 vs EPF10K250EBC600-3 Comparaison
Comparaison détaillée côte à côte de EPF10K200EBC600-2 par Intel et EPF10K250EBC600-3 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPF10K200EBC600-2 | EPF10K250EBC600-3 |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $198,00 | $205,00 |
| Series | FLEX-10KE | — |
| Logic Family | CMOS (SRAM-based) | — |
| Process Technology | 0.30 µm CMOS | SRAM-based CMOS |
| Typical Gate Count | 200,000 gates | — |
| Logic Elements (LEs) | 9984 | — |
| Logic Array Blocks (LABs) | 1248 | — |
| Embedded Memory (EAB) | 98304 bits (96 Kbits) | — |
| Maximum User I/O | 470 pins | 470 |
| Propagation Delay | 0.4 ns | — |
| Tension d'alimentation | 2.3 V to 2.7 V (core), 2.5/3.3 V (I/O) | — |
| I/O Standards | LVTTL, LVCMOS, PCI, GTL+ | — |
| Package Type | 600-ball BGA (BGA-600) | — |
| Package Dimensions | 45 × 45 mm | — |
| Ball Pitch | 1.27 mm | — |
| Package Height | 1.1 mm max | — |
| Température de fonctionnement | 0°C to +70°C (Commercial) | [DATA_NEEDED: operating temperature range] |
| Type de montage | Surface Mount | — |
| Configuration Method | JTAG (IEEE 1149.1), EPC2 serial PROM | — |
| Part Status | Obsolete | — |
| Statut RoHS | unknown | — |
| Family | — | FLEX 10KE |
| Logic Elements | — | 12,160 LEs |
| Typical Gates | — | 250,000 |
| Embedded Array Blocks (EABs) | — | 12 (each 2 Kbits) |
| Total Embedded Memory | — | 24 Kbits (RAM) |
| PLLs (Phase-Locked Loops) | — | 4 |
| Dedicated Clock Inputs | — | 6 |
| Speed Grade | — | -3 |
| Core Supply Voltage | — | 3.3 V |
| I/O Supply Voltage | — | 3.3 V (5 V tolerant) |
| Boîtier | — | 600-ball FineLine BGA |
| Configuration Mode | — | Passive Serial / Passive Parallel / JTAG |
| Boundary Scan | — | IEEE 1149.1 (JTAG) |