EPM3064ATC44-7 vs EPM3064ATC44-10N Comparación
Comparación detallada lado a lado de EPM3064ATC44-7 por Altera y EPM3064ATC44-10N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM3064ATC44-7 | EPM3064ATC44-10N |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $4,20 | $5,10 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 64 | — |
| Logic Array Blocks | 4 | — |
| Usable Gates | 1.25K | 1250 |
| User I/O Pins | 34 | 34 |
| Recuento de pines | 44 | — |
| Encapsulado | TQFP-44 | TQFP-44 (10x10 mm) |
| Speed Grade | -7 (7.5 ns tPD) | — |
| Pin-to-Pin Propagation Delay | 7.5 ns | — |
| Maximum Counter Frequency | 192.3 MHz | 192.3 MHz |
| Supply Voltage (Core) | 3.3 V | — |
| I/O Logic Compatibility | 5.0 V / 3.3 V / 2.5 V (MultiVolt) | — |
| Programming Interface | IEEE Std. 1149.1 JTAG (ISP) | — |
| Process Technology | CMOS EEPROM | — |
| Temperatura de funcionamiento | 0C to +70C (Commercial) | 0C to +70C (commercial) |
| Tipo de montaje | Surface Mount | Surface Mount |
| Estado RoHS | unknown | Compliant |
| Macro Cells | — | 64 |
| Logic Array Blocks (LABs) | — | 4 |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Standard | — | MultiVolt (mixed 1.5 V / 1.8 V / 2.5 V / 3.3 V) |
| Configuration Memory | — | EEPROM (non-volatile) |
| In-System Programming | — | IEEE Std. 1532 compliant |
| Boundary-Scan Test | — | IEEE Std. 1149.1 (JTAG) compliant |
| Pin-Locking | — | Yes (across design iterations) |