EPM3064ATC44-7 vs EPM3064ATC44-10N 对比

详细并排对比 EPM3064ATC44-7 出自 Altera 和 EPM3064ATC44-10N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EPM3064ATC44-10N EPM3064ATC44-10N - 64-Macro Cell MAX 3000A CPLD | Altera

EPM3064ATC44-10N - 64-Macro Cell MAX 3000A CPLD | Altera

EPM3064ATC44-10N ✓ 量产中

规格对比

参数 EPM3064ATC44-7 EPM3064ATC44-10N
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 有效
库存状态 有库存 有库存
单价(USD) $4.20 $5.10
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 64 —
Logic Array Blocks 4 —
Usable Gates 1.25K 1250
User I/O Pins 34 34
引脚数量 44 —
封装 TQFP-44 TQFP-44 (10x10 mm)
Speed Grade -7 (7.5 ns tPD) —
Pin-to-Pin Propagation Delay 7.5 ns —
Maximum Counter Frequency 192.3 MHz 192.3 MHz
Supply Voltage (Core) 3.3 V —
I/O Logic Compatibility 5.0 V / 3.3 V / 2.5 V (MultiVolt) —
Programming Interface IEEE Std. 1149.1 JTAG (ISP) —
Process Technology CMOS EEPROM —
工作温度 0C to +70C (Commercial) 0C to +70C (commercial)
安装类型 Surface Mount Surface Mount
RoHS 状态 unknown Compliant
Macro Cells — 64
Logic Array Blocks (LABs) — 4
Pin-to-Pin Delay (tPD) — 10 ns
Supply Voltage (VCCINT) — 3.3 V
I/O Standard — MultiVolt (mixed 1.5 V / 1.8 V / 2.5 V / 3.3 V)
Configuration Memory — EEPROM (non-volatile)
In-System Programming — IEEE Std. 1532 compliant
Boundary-Scan Test — IEEE Std. 1149.1 (JTAG) compliant
Pin-Locking — Yes (across design iterations)

数据手册与资源

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