EPM3128ATC100-5 vs EPM3128ATI100-5N Comparación
Comparación detallada lado a lado de EPM3128ATC100-5 por Intel y EPM3128ATI100-5N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
EPM3128ATI100-5N - MAX 3000A CPLD, 128 Macrocells, TQFP-100 | Intel / Altera
EPM3128ATI100-5N ✓ ActivoComparación de especificaciones
| Parámetro | EPM3128ATC100-5 | EPM3128ATI100-5N |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $15,43 | $11,45 |
| Series | MAX 3000A | — |
| Family | CPLD - MAX 3000A | MAX 3000A |
| Macrocells | 128 | 128 |
| Usable Gates | 2,500 | — |
| User I/Os | 80 | — |
| Dedicated Inputs | 4 | — |
| Pin-to-Pin Delay (tpd) | 5 ns (commercial); 7.5 ns | — |
| Maximum Frequency (fCNT) | 192.3 MHz | — |
| Supply Voltage (VCCINT/VCCIO) | 3.3 V | — |
| Output Drive Voltage | 2.5 V or 3.3 V (programmable) | — |
| Input Tolerance | 2.5 V, 3.3 V, 5.0 V tolerant | — |
| Program Memory Type | EEPROM | — |
| In-System Programmability | Yes, IEEE Std. 1532 compliant | — |
| JTAG Boundary Scan | Yes, IEEE Std. 1149.1 | — |
| Temperatura de funcionamiento | 0 °C to 70 °C (Commercial) | -40C to +85C (Industrial) |
| Encapsulado | 100-pin TQFP (Fine Line) | 100-pin TQFP |
| Tipo de montaje | Surface Mount | Surface Mount |
| Logic Family | CMOS | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | Compliant (lead-free TQFP package) |
| Process Technology | CMOS EEPROM | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Array Blocks (LABs) | — | 8 (16 macrocells per LAB) |
| User I/O Pins | — | 80 |
| Pin-to-Pin Delay (tPD) | — | 5.0 ns |
| Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Standard | — | 3.3 V LVCMOS / LVTTL, 5.0 V tolerant inputs |
| Programming Method | — | In-System Programmable via IEEE Std. 1532 (JTAG) |
| Configuration Memory | — | Non-volatile EEPROM |
| JTAG Support | — | IEEE 1149.1 boundary scan |