EPM3512AFC256-10 vs EPM3512AFC256-10N Comparación
Comparación detallada lado a lado de EPM3512AFC256-10 por Altera y EPM3512AFC256-10N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM3512AFC256-10 | EPM3512AFC256-10N |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $17,50 | $43,22 |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 512 | 512 |
| Logic Array Blocks (LABs) | 16 | [DATA_NEEDED: number of LABs] |
| Usable Gates | 10,000 | 10000 |
| Maximum I/O Pins | 208 | — |
| Pin-to-Pin Delay (tPD) | 10 ns | 10 ns |
| Maximum Counter Frequency | 87 MHz | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Voltage Tolerance | 5-V tolerant | — |
| Programmable Technology | CMOS EEPROM | — |
| In-System Programmability | Yes (IEEE Std. 1149.1 JTAG / IEEE Std. 1532) | — |
| Encapsulado | 256-pin FBGA | 256-ball FBGA (17 mm x 17 mm) |
| Rango de temperatura de funcionamiento | [DATA_NEEDED: industrial/commercial operating temperature range] | — |
| Recuento de pines | 256 | — |
| Tipo de montaje | Surface Mount | Surface Mount (BGA) |
| Estado RoHS | unknown | [DATA_NEEDED: RoHS status] |
| Architecture | MAX (Multiple Array matriX) EEPROM-based | — |
| User I/O Pins | — | 208 |
| Operating Frequency (fMAX) | — | [DATA_NEEDED: fMAX MHz] |
| Setup Time (tSU) | — | 4.5 ns |
| VCCINT (Core Supply) | — | 3.3 V |
| VCCIO (I/O Supply) | — | 3.3 V or 2.5 V |
| Technology | — | CMOS EEPROM-based, non-volatile |
| Operating Temperature (Commercial) | — | 0 C to +70 C |
| ISP Interface | — | IEEE Std. 1149.1 JTAG, IEEE Std. 1532 |
| Nivel MSL | — | [DATA_NEEDED: MSL rating] |