EPM3512AFC256-10 vs EPM3512AFC256-10N 对比

详细并排对比 EPM3512AFC256-10 出自 Altera 和 EPM3512AFC256-10N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM3512AFC256-10 EPM3512AFC256-10N
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $17.50 $43.22
Family MAX 3000A MAX 3000A
Macrocells 512 512
Logic Array Blocks (LABs) 16 [DATA_NEEDED: number of LABs]
Usable Gates 10,000 10000
Maximum I/O Pins 208 —
Pin-to-Pin Delay (tPD) 10 ns 10 ns
Maximum Counter Frequency 87 MHz —
Supply Voltage (VCCINT) 3.3 V —
I/O Voltage Tolerance 5-V tolerant —
Programmable Technology CMOS EEPROM —
In-System Programmability Yes (IEEE Std. 1149.1 JTAG / IEEE Std. 1532) —
封装 256-pin FBGA 256-ball FBGA (17 mm x 17 mm)
工作温度范围 [DATA_NEEDED: industrial/commercial operating temperature range] —
引脚数量 256 —
安装类型 Surface Mount Surface Mount (BGA)
RoHS 状态 unknown [DATA_NEEDED: RoHS status]
Architecture MAX (Multiple Array matriX) EEPROM-based —
User I/O Pins — 208
Operating Frequency (fMAX) — [DATA_NEEDED: fMAX MHz]
Setup Time (tSU) — 4.5 ns
VCCINT (Core Supply) — 3.3 V
VCCIO (I/O Supply) — 3.3 V or 2.5 V
Technology — CMOS EEPROM-based, non-volatile
Operating Temperature (Commercial) — 0 C to +70 C
ISP Interface — IEEE Std. 1149.1 JTAG, IEEE Std. 1532
MSL 等级 — [DATA_NEEDED: MSL rating]

数据手册与资源

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