EPM3512AFC256-2 vs EPM3512AFC256-19 Comparación
Comparación detallada lado a lado de EPM3512AFC256-2 por Altera y EPM3512AFC256-19 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM3512AFC256-2 | EPM3512AFC256-19 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $14,85 | $10,85 |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 512 | 512 |
| Logic Array Blocks (LABs) | 16 | 16 |
| Maximum User I/O Pins | 212 | — |
| Propagation Delay (tPD, -2 grade) | [DATA_NEEDED: tPD ns] | — |
| Maximum Operating Frequency | [DATA_NEEDED: fMAX MHz] | 80 MHz |
| Core Supply Voltage | 3.3 V | — |
| I/O Output Drive Voltage | 2.5 V or 3.3 V (MultiVolt) | — |
| Input Tolerance | 2.5 V, 3.3 V, 5.0 V tolerant | — |
| Encapsulado | BGA-256 (FineLine BGA) | 256-ball FineLine BGA (FC) |
| Ball Pitch | 1.0 mm | — |
| Programming Interface | JTAG (IEEE Std 1149.1) / ByteBlaster | JTAG (IEEE 1149.1) / ISP (IEEE 1532) |
| Process Technology | 0.30 um CMOS EEPROM | 0.30 µm CMOS EEPROM |
| Temperatura de funcionamiento | 0C to +70C (commercial) | -40C to +85C (industrial) |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Speed Grade | -2 | -19 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 10000 |
| Pin-to-Pin Delay (tPD) | — | 7.5 ns |
| User I/O Pins | — | 208 |
| Supply Voltage VCCINT | — | 3.3 V |
| I/O Supply Voltage VCCIO | — | 2.5 V or 3.3 V (5.0 V tolerant inputs) |
| Non-volatile Configuration | — | Yes (EEPROM-based) |
| Tipo de montaje | — | Surface Mount |