EPM3512AFC256-2 vs EPM3512AFC256-19 Comparison

Detailed side-by-side comparison of EPM3512AFC256-2 by Altera and EPM3512AFC256-19 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3512AFC256-2 EPM3512AFC256-19
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $14.85 $10.85
Family MAX 3000A MAX 3000A
Macrocells 512 512
Logic Array Blocks (LABs) 16 16
Maximum User I/O Pins 212 β€”
Propagation Delay (tPD, -2 grade) [DATA_NEEDED: tPD ns] β€”
Maximum Operating Frequency [DATA_NEEDED: fMAX MHz] 80 MHz
Core Supply Voltage 3.3 V β€”
I/O Output Drive Voltage 2.5 V or 3.3 V (MultiVolt) β€”
Input Tolerance 2.5 V, 3.3 V, 5.0 V tolerant β€”
Package BGA-256 (FineLine BGA) 256-ball FineLine BGA (FC)
Ball Pitch 1.0 mm β€”
Programming Interface JTAG (IEEE Std 1149.1) / ByteBlaster JTAG (IEEE 1149.1) / ISP (IEEE 1532)
Process Technology 0.30 um CMOS EEPROM 0.30 Β΅m CMOS EEPROM
Operating Temperature 0C to +70C (commercial) -40C to +85C (industrial)
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Speed Grade -2 -19
Device Type β€” CPLD (Complex Programmable Logic Device)
Usable Gates β€” 10000
Pin-to-Pin Delay (tPD) β€” 7.5 ns
User I/O Pins β€” 208
Supply Voltage VCCINT β€” 3.3 V
I/O Supply Voltage VCCIO β€” 2.5 V or 3.3 V (5.0 V tolerant inputs)
Non-volatile Configuration β€” Yes (EEPROM-based)
Mounting Type β€” Surface Mount

Datasheets & Resources

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