EPM3512AFC256-3N vs EPM3512AFC256-10N Comparación
Comparación detallada lado a lado de EPM3512AFC256-3N por Altera y EPM3512AFC256-10N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM3512AFC256-3N | EPM3512AFC256-10N |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Activo | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $23,40 | $43,22 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 512 | 512 |
| Usable Gates | 10,000 | 10000 |
| Logic Array Blocks (LABs) | 16 | [DATA_NEEDED: number of LABs] |
| Maximum Operating Frequency | 116.3 MHz | — |
| Pin-to-Pin Delay (tPD) | 3.5 ns (speed grade -3) | 10 ns |
| Speed Grade | -3 (slowest in family) | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (MultiVolt) | — |
| Encapsulado | 256-ball FineLine BGA (FC-256) | 256-ball FBGA (17 mm x 17 mm) |
| Tipo de montaje | Surface Mount | Surface Mount (BGA) |
| Programming Interface | JTAG (IEEE 1149.1) / IEEE Std. 1532 ISP | — |
| Configuration Memory | Non-volatile EEPROM | — |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature grade] | — |
| Estado RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| User I/O Pins | — | 208 |
| Operating Frequency (fMAX) | — | [DATA_NEEDED: fMAX MHz] |
| Setup Time (tSU) | — | 4.5 ns |
| VCCINT (Core Supply) | — | 3.3 V |
| VCCIO (I/O Supply) | — | 3.3 V or 2.5 V |
| Technology | — | CMOS EEPROM-based, non-volatile |
| Operating Temperature (Commercial) | — | 0 C to +70 C |
| ISP Interface | — | IEEE Std. 1149.1 JTAG, IEEE Std. 1532 |
| Nivel MSL | — | [DATA_NEEDED: MSL rating] |