EPM3512AFC256-3N vs EPM3512AFC256-10N 对比

详细并排对比 EPM3512AFC256-3N 出自 Altera 和 EPM3512AFC256-10N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EPM3512AFC256-3N EPM3512AFC256-3N - MAX 3000A CPLD 512 Macrocells | Altera

EPM3512AFC256-3N - MAX 3000A CPLD 512 Macrocells | Altera

EPM3512AFC256-3N ✓ 量产中

规格对比

参数 EPM3512AFC256-3N EPM3512AFC256-10N
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 有效 Obsolete
库存状态 有库存 有库存
单价(USD) $23.40 $43.22
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) —
Macrocells 512 512
Usable Gates 10,000 10000
Logic Array Blocks (LABs) 16 [DATA_NEEDED: number of LABs]
Maximum Operating Frequency 116.3 MHz —
Pin-to-Pin Delay (tPD) 3.5 ns (speed grade -3) 10 ns
Speed Grade -3 (slowest in family) —
Core Supply Voltage (VCCINT) 3.3 V —
I/O Supply Voltage (VCCIO) 2.5 V / 3.3 V / 5.0 V (MultiVolt) —
封装 256-ball FineLine BGA (FC-256) 256-ball FBGA (17 mm x 17 mm)
安装类型 Surface Mount Surface Mount (BGA)
Programming Interface JTAG (IEEE 1149.1) / IEEE Std. 1532 ISP —
Configuration Memory Non-volatile EEPROM —
工作温度 [DATA_NEEDED: operating temperature grade] —
RoHS 状态 [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS status]
User I/O Pins — 208
Operating Frequency (fMAX) — [DATA_NEEDED: fMAX MHz]
Setup Time (tSU) — 4.5 ns
VCCINT (Core Supply) — 3.3 V
VCCIO (I/O Supply) — 3.3 V or 2.5 V
Technology — CMOS EEPROM-based, non-volatile
Operating Temperature (Commercial) — 0 C to +70 C
ISP Interface — IEEE Std. 1149.1 JTAG, IEEE Std. 1532
MSL 等级 — [DATA_NEEDED: MSL rating]

数据手册与资源

浏览全部产品 创建 BOM 获取报价