EPM3512AFC256-3N vs EPM3512AFC256-2 Comparación
Comparación detallada lado a lado de EPM3512AFC256-3N por Altera y EPM3512AFC256-2 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM3512AFC256-3N | EPM3512AFC256-2 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Activo | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $23,40 | $14,85 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 512 | 512 |
| Usable Gates | 10,000 | — |
| Logic Array Blocks (LABs) | 16 | 16 |
| Maximum Operating Frequency | 116.3 MHz | [DATA_NEEDED: fMAX MHz] |
| Pin-to-Pin Delay (tPD) | 3.5 ns (speed grade -3) | — |
| Speed Grade | -3 (slowest in family) | -2 |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (MultiVolt) | — |
| Encapsulado | 256-ball FineLine BGA (FC-256) | BGA-256 (FineLine BGA) |
| Tipo de montaje | Surface Mount | — |
| Programming Interface | JTAG (IEEE 1149.1) / IEEE Std. 1532 ISP | JTAG (IEEE Std 1149.1) / ByteBlaster |
| Configuration Memory | Non-volatile EEPROM | — |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature grade] | 0C to +70C (commercial) |
| Estado RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Maximum User I/O Pins | — | 212 |
| Propagation Delay (tPD, -2 grade) | — | [DATA_NEEDED: tPD ns] |
| Core Supply Voltage | — | 3.3 V |
| I/O Output Drive Voltage | — | 2.5 V or 3.3 V (MultiVolt) |
| Input Tolerance | — | 2.5 V, 3.3 V, 5.0 V tolerant |
| Ball Pitch | — | 1.0 mm |
| Process Technology | — | 0.30 um CMOS EEPROM |