EPM5128JC-2 vs EPM5128JC Comparación
Comparación detallada lado a lado de EPM5128JC-2 por Altera y EPM5128JC por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM5128JC-2 | EPM5128JC |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $21,75 | $9,75 |
| Family | MAX 5000 | — |
| Device Type | UV-Erasable Programmable Logic Device (PLD) | EPLD / CPLD |
| Macrocells | 128 | — |
| Dedicated Inputs | 7 | 8 |
| Propagation Delay (tPD) | 45 ns (max) | 35 ns |
| Maximum Counter Frequency (fCNT) | 50 MHz | — |
| Input Setup Time (tSU) | 7.5 ns | — |
| Output Drive Current (IOH/IOL) | 12 mA DC | — |
| Process Technology | CMOS | CMOS EPROM |
| Encapsulado | 68-pin CQCC (Ceramic Quad Flat Pack), windowed | — |
| Tipo de montaje | Surface Mount | Surface Mount (PLCC socket or solder) |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | Commercial 0C to +70C |
| Tensión de alimentación | 5 V (nominal) | — |
| Program/Erase Method | UV (ceramic window) | — |
| Erase/Program Cycles | [DATA_NEEDED: minimum erase/program cycles] | — |
| Estado RoHS | Non-compliant (ceramic windowed package contains lead-bearing solder) | [DATA_NEEDED: RoHS status - legacy part] |
| Logic Family | TTL-compatible I/O | — |
| Product Family | — | MAX 5000 |
| Macrocell Count | — | 128 |
| Logic Elements | — | Programmable AND/OR/XOR array |
| Supply Voltage (VCC) | — | 5 V (typical) |
| Número de pines | — | 68 |
| Package Type | — | PLCC-68 (JLCC) ceramic, J-leaded |
| User I/O Pins | — | [DATA_NEEDED: user I/O pin count] |
| Configuration Memory | — | UV-erasable EPROM (windowed package) |
| Programming Interface | — | Altera MAX+PLUS II / A+PLUS / legacy programmer |
| Boundary Scan | — | JTAG IEEE 1149.1 (family feature) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |