EPM5128JC-2 vs EPM5128JC 비교
다음의 상세 나란히 비교: EPM5128JC-2 제조: Altera 및 EPM5128JC 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EPM5128JC-2 | EPM5128JC |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $21.75 | $9.75 |
| Family | MAX 5000 | — |
| Device Type | UV-Erasable Programmable Logic Device (PLD) | EPLD / CPLD |
| Macrocells | 128 | — |
| Dedicated Inputs | 7 | 8 |
| Propagation Delay (tPD) | 45 ns (max) | 35 ns |
| Maximum Counter Frequency (fCNT) | 50 MHz | — |
| Input Setup Time (tSU) | 7.5 ns | — |
| Output Drive Current (IOH/IOL) | 12 mA DC | — |
| Process Technology | CMOS | CMOS EPROM |
| 패키지 | 68-pin CQCC (Ceramic Quad Flat Pack), windowed | — |
| 실장 유형 | Surface Mount | Surface Mount (PLCC socket or solder) |
| 동작 온도 | [DATA_NEEDED: operating temperature range] | Commercial 0C to +70C |
| 공급 전압 | 5 V (nominal) | — |
| Program/Erase Method | UV (ceramic window) | — |
| Erase/Program Cycles | [DATA_NEEDED: minimum erase/program cycles] | — |
| RoHS 상태 | Non-compliant (ceramic windowed package contains lead-bearing solder) | [DATA_NEEDED: RoHS status - legacy part] |
| Logic Family | TTL-compatible I/O | — |
| Product Family | — | MAX 5000 |
| Macrocell Count | — | 128 |
| Logic Elements | — | Programmable AND/OR/XOR array |
| Supply Voltage (VCC) | — | 5 V (typical) |
| 핀 수 | — | 68 |
| Package Type | — | PLCC-68 (JLCC) ceramic, J-leaded |
| User I/O Pins | — | [DATA_NEEDED: user I/O pin count] |
| Configuration Memory | — | UV-erasable EPROM (windowed package) |
| Programming Interface | — | Altera MAX+PLUS II / A+PLUS / legacy programmer |
| Boundary Scan | — | JTAG IEEE 1149.1 (family feature) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |