EPM5128JC vs EPM5128JC-2 Comparación
Comparación detallada lado a lado de EPM5128JC por Altera y EPM5128JC-2 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM5128JC | EPM5128JC-2 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,75 | $21,75 |
| Product Family | MAX 5000 | — |
| Device Type | EPLD / CPLD | UV-Erasable Programmable Logic Device (PLD) |
| Macrocell Count | 128 | — |
| Propagation Delay (tPD) | 35 ns | 45 ns (max) |
| Logic Elements | Programmable AND/OR/XOR array | — |
| Supply Voltage (VCC) | 5 V (typical) | — |
| Número de pines | 68 | — |
| Package Type | PLCC-68 (JLCC) ceramic, J-leaded | — |
| Dedicated Inputs | 8 | 7 |
| User I/O Pins | [DATA_NEEDED: user I/O pin count] | — |
| Configuration Memory | UV-erasable EPROM (windowed package) | — |
| Programming Interface | Altera MAX+PLUS II / A+PLUS / legacy programmer | — |
| Temperatura de funcionamiento | Commercial 0C to +70C | [DATA_NEEDED: operating temperature range] |
| Tipo de montaje | Surface Mount (PLCC socket or solder) | Surface Mount |
| Boundary Scan | JTAG IEEE 1149.1 (family feature) | — |
| Process Technology | CMOS EPROM | CMOS |
| Estado RoHS | [DATA_NEEDED: RoHS status - legacy part] | Non-compliant (ceramic windowed package contains lead-bearing solder) |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Family | — | MAX 5000 |
| Macrocells | — | 128 |
| Maximum Counter Frequency (fCNT) | — | 50 MHz |
| Input Setup Time (tSU) | — | 7.5 ns |
| Output Drive Current (IOH/IOL) | — | 12 mA DC |
| Encapsulado | — | 68-pin CQCC (Ceramic Quad Flat Pack), windowed |
| Tensión de alimentación | — | 5 V (nominal) |
| Program/Erase Method | — | UV (ceramic window) |
| Erase/Program Cycles | — | [DATA_NEEDED: minimum erase/program cycles] |
| Logic Family | — | TTL-compatible I/O |