EPM5128JC vs EPM5128JC-2 비교
다음의 상세 나란히 비교: EPM5128JC 제조: Altera 및 EPM5128JC-2 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EPM5128JC | EPM5128JC-2 |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $9.75 | $21.75 |
| Product Family | MAX 5000 | — |
| Device Type | EPLD / CPLD | UV-Erasable Programmable Logic Device (PLD) |
| Macrocell Count | 128 | — |
| Propagation Delay (tPD) | 35 ns | 45 ns (max) |
| Logic Elements | Programmable AND/OR/XOR array | — |
| Supply Voltage (VCC) | 5 V (typical) | — |
| 핀 수 | 68 | — |
| Package Type | PLCC-68 (JLCC) ceramic, J-leaded | — |
| Dedicated Inputs | 8 | 7 |
| User I/O Pins | [DATA_NEEDED: user I/O pin count] | — |
| Configuration Memory | UV-erasable EPROM (windowed package) | — |
| Programming Interface | Altera MAX+PLUS II / A+PLUS / legacy programmer | — |
| 동작 온도 | Commercial 0C to +70C | [DATA_NEEDED: operating temperature range] |
| 실장 유형 | Surface Mount (PLCC socket or solder) | Surface Mount |
| Boundary Scan | JTAG IEEE 1149.1 (family feature) | — |
| Process Technology | CMOS EPROM | CMOS |
| RoHS 상태 | [DATA_NEEDED: RoHS status - legacy part] | Non-compliant (ceramic windowed package contains lead-bearing solder) |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Family | — | MAX 5000 |
| Macrocells | — | 128 |
| Maximum Counter Frequency (fCNT) | — | 50 MHz |
| Input Setup Time (tSU) | — | 7.5 ns |
| Output Drive Current (IOH/IOL) | — | 12 mA DC |
| 패키지 | — | 68-pin CQCC (Ceramic Quad Flat Pack), windowed |
| 공급 전압 | — | 5 V (nominal) |
| Program/Erase Method | — | UV (ceramic window) |
| Erase/Program Cycles | — | [DATA_NEEDED: minimum erase/program cycles] |
| Logic Family | — | TTL-compatible I/O |