EPM5128JC vs EPM5128JC-2 Comparison

Detailed side-by-side comparison of EPM5128JC by Altera and EPM5128JC-2 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM5128JC-2

EPM5128JC-2 - 128-Macrocell UV PLD, 45ns, CQCC-68 | Altera

EPM5128JC-2 Obsolete

Specification Comparison

Parameter EPM5128JC EPM5128JC-2
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $9.75 $21.75
Product Family MAX 5000 β€”
Device Type EPLD / CPLD UV-Erasable Programmable Logic Device (PLD)
Macrocell Count 128 β€”
Propagation Delay (tPD) 35 ns 45 ns (max)
Logic Elements Programmable AND/OR/XOR array β€”
Supply Voltage (VCC) 5 V (typical) β€”
Number of Pins 68 β€”
Package Type PLCC-68 (JLCC) ceramic, J-leaded β€”
Dedicated Inputs 8 7
User I/O Pins [DATA_NEEDED: user I/O pin count] β€”
Configuration Memory UV-erasable EPROM (windowed package) β€”
Programming Interface Altera MAX+PLUS II / A+PLUS / legacy programmer β€”
Operating Temperature Commercial 0C to +70C [DATA_NEEDED: operating temperature range]
Mounting Type Surface Mount (PLCC socket or solder) Surface Mount
Boundary Scan JTAG IEEE 1149.1 (family feature) β€”
Process Technology CMOS EPROM CMOS
RoHS Status [DATA_NEEDED: RoHS status - legacy part] Non-compliant (ceramic windowed package contains lead-bearing solder)
Lead-Free [DATA_NEEDED: lead-free status] β€”
Family β€” MAX 5000
Macrocells β€” 128
Maximum Counter Frequency (fCNT) β€” 50 MHz
Input Setup Time (tSU) β€” 7.5 ns
Output Drive Current (IOH/IOL) β€” 12 mA DC
Package β€” 68-pin CQCC (Ceramic Quad Flat Pack), windowed
Supply Voltage β€” 5 V (nominal)
Program/Erase Method β€” UV (ceramic window)
Erase/Program Cycles β€” [DATA_NEEDED: minimum erase/program cycles]
Logic Family β€” TTL-compatible I/O

Datasheets & Resources

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