EPM5192GI84 vs EPM5192GC1 Comparación
Comparación detallada lado a lado de EPM5192GI84 por Altera y EPM5192GC1 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM5192GI84 | EPM5192GC1 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $19,80 | $24,50 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | UV-Erasable / OTP Complex PLD (CPLD) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 192 | — |
| Logic Array Blocks | [DATA_NEEDED: number of LABs] | — |
| Encapsulado | 84-pin PGA (WPGA, square, through-hole, pin/peg terminals) | — |
| Package Code | WPGA | — |
| Operating Voltage (VCC) | 5 V (typical) | — |
| I/O Logic Compatibility | TTL | — |
| Temperature Grade | Industrial | — |
| Programmable Flip-Flop Modes | D, T, JK, SR | — |
| Programmability | UV-erasable (windowed) / OTP | — |
| Programming File Format | JEDEC map via MAX+PLUS II / A+PLUS | — |
| Propagation Delay | [DATA_NEEDED: tPD in ns] | [DATA_NEEDED: tpd specification] |
| Max User I/O Pins | [DATA_NEEDED: usable I/O count for this package] | — |
| Rango de temperatura de funcionamiento | -40 C to +85 C (industrial) | — |
| Tipo de montaje | Through-Hole (PGA socket or PCB pin/peg) | Through-hole (PGA) |
| Estado RoHS | [DATA_NEEDED: most legacy PGA parts are non-RoHS] | unknown |
| Lead-Free | [DATA_NEEDED: legacy part, likely contains lead] | — |
| Number of Terminals | 84 | — |
| Terminal Form | PIN/PEG | — |
| Package Shape | SQUARE | — |
| Macro Cells | — | 192 |
| Usable Gates | — | 3,750 |
| Maximum Operating Frequency | — | 62.5 MHz |
| Supply Voltage (VCC) | — | 5 V |
| Programming Technology | — | UV-Erasable / OTP EPROM |
| Package Type | — | Ceramic PGA (Pin Grid Array) |
| Logic Elements | — | 192 macrocells with AND/OR array |
| Process Technology | — | EPROM-based CMOS |
| Temperatura de funcionamiento | — | [DATA_NEEDED: operating temperature range] |
| Número de pines | — | [DATA_NEEDED: pin count for GC1 PGA package] |
| Development Tool | — | Altera MAX+PLUS II |