EPM5192GI84 vs EPM5192GC1 Comparaison
Comparaison détaillée côte à côte de EPM5192GI84 par Altera et EPM5192GC1 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM5192GI84 | EPM5192GC1 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $19,80 | $24,50 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | UV-Erasable / OTP Complex PLD (CPLD) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 192 | — |
| Logic Array Blocks | [DATA_NEEDED: number of LABs] | — |
| Boîtier | 84-pin PGA (WPGA, square, through-hole, pin/peg terminals) | — |
| Package Code | WPGA | — |
| Operating Voltage (VCC) | 5 V (typical) | — |
| I/O Logic Compatibility | TTL | — |
| Temperature Grade | Industrial | — |
| Programmable Flip-Flop Modes | D, T, JK, SR | — |
| Programmability | UV-erasable (windowed) / OTP | — |
| Programming File Format | JEDEC map via MAX+PLUS II / A+PLUS | — |
| Propagation Delay | [DATA_NEEDED: tPD in ns] | [DATA_NEEDED: tpd specification] |
| Max User I/O Pins | [DATA_NEEDED: usable I/O count for this package] | — |
| Plage de température de fonctionnement | -40 C to +85 C (industrial) | — |
| Type de montage | Through-Hole (PGA socket or PCB pin/peg) | Through-hole (PGA) |
| Statut RoHS | [DATA_NEEDED: most legacy PGA parts are non-RoHS] | unknown |
| Lead-Free | [DATA_NEEDED: legacy part, likely contains lead] | — |
| Number of Terminals | 84 | — |
| Terminal Form | PIN/PEG | — |
| Package Shape | SQUARE | — |
| Macro Cells | — | 192 |
| Usable Gates | — | 3,750 |
| Maximum Operating Frequency | — | 62.5 MHz |
| Supply Voltage (VCC) | — | 5 V |
| Programming Technology | — | UV-Erasable / OTP EPROM |
| Package Type | — | Ceramic PGA (Pin Grid Array) |
| Logic Elements | — | 192 macrocells with AND/OR array |
| Process Technology | — | EPROM-based CMOS |
| Température de fonctionnement | — | [DATA_NEEDED: operating temperature range] |
| Nombre de broches | — | [DATA_NEEDED: pin count for GC1 PGA package] |
| Development Tool | — | Altera MAX+PLUS II |