EPM5192JC-ES vs EPM5192JC1 Comparación
Comparación detallada lado a lado de EPM5192JC-ES por Intel y EPM5192JC1 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM5192JC-ES | EPM5192JC1 |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $16,45 | $48,30 |
| Device Family | MAX 5000 | — |
| Device Type | CPLD (EPLD) | — |
| Macrocells | 192 | — |
| Logic Array Blocks (LABs) | 12 | — |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Configuration Memory | EPROM (UV-erasable, one-time programmable for JC-ES) | — |
| Encapsulado | 84-pin PLCC (J-lead, CQCC, JEDEC S-CQCC-J84) | [DATA_NEEDED: exact package from datasheet] |
| Tipo de montaje | Surface Mount | [DATA_NEEDED: surface mount or through-hole] |
| Technology | CMOS | — |
| Programming | Altera MAX+PLUS II or compatible programmer | — |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature range for ES grade] | [DATA_NEEDED: operating temp range] |
| Tensión de alimentación | [DATA_NEEDED: VCC nominal] | — |
| User I/O Pins | [DATA_NEEDED: user I/O count for JC-ES in PLCC-84] | — |
| Estado RoHS | [DATA_NEEDED: RoHS compliance] | unknown |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Nivel MSL | [DATA_NEEDED: MSL rating] | — |
| Note | Datasheet source: Altera MAX 5000 family document, 52 pages | — |
| Family | — | MAX 5000 (MAX 5xxx CPLD) |
| Manufacturer | — | Intel (formerly Altera Corporation) |
| Macro Cells | — | 192 |
| Usable Gates | — | 3750 |
| Maximum Operating Frequency | — | 62.5 MHz |
| Supply Voltage (VCC) | — | 5 V (nominal) |
| Process Technology | — | 0.5 µm CMOS, UV-erasable EPROM |
| Propagation Delay (typ) | — | [DATA_NEEDED: propagation delay in ns] |
| I/O Pins | — | [DATA_NEEDED: I/O pin count] |
| Programming Interface | — | JTAG-compatible (Altera MAX 5xxx) |
| Logic Blocks (LABs) | — | 24 (8 macrocells per LAB) |
| AEC-Q100 | — | not_applicable |
| Lifecycle | — | Obsolete - last-time-buy stock only at franchised distributors |